The present invention relates to semiconductor memories. In particular, the present invention relates to static random access memories (SRAM) and dynamic random access memories (DRAM).
The conventional method for column address decoding is to provide column decoders spread all the way across the chip. That is, where a subarray has 128 columns, 7 buss lines will typically be provided to carry the corresponding address bits across the chip, and a separate decoder, connected to the 7 buss lines, will be provided for each column. This is adequately fast, but occupies a tremendous amount of space with this plethora of column decoders.
Thus it is an object of the present invention to provide a semiconductor memory wherein less space is required for routing of the column address lines and for column address logic.
A further difficulty with the prior art is that the column address decoders expand the total area of the chip. That is, these are not included in waste space, but lengthen one dimension of the chip, and therefore require more chip area. This leads to higher cost and lower yield, as is well known to those skilled in the art.
Thus it is an object of the present invention to provide a semiconductor random access memory wherein the column address decoding function requires only a minimal amount of extra chip area.
This prior art problem has been particularly obstreperous in the area of static random access memories (SRAMs). Typically these are very high speed memories in which the column pitch is somewhat larger than the column pitch for DRAM memories at comparable stages of the art. The availability of this extra pitch and the requirement of higher speed has made it particularly tempting for designers to use per-column decode all across the chip. However, increase in total chip area is as disastrous to cost and yield in the SRAM art as in the DRAM art.
Thus it is an object of the present invention to provide an SRAM having a column address decode implementation which only minimaly increases the total area of the chip.
It is further object of the present invention to provide a static random access memory having an address decode function implementation which only minimaly increases the total area of the chip, and which does not slow down the speed of the chip.
The difficulty in getting around the per-column decoding implementation of the prior art is that, if the column lines were decoded at the edge of the array, an immense amount of space would be wasted in buss lines. For example, to run 128 buss lines across the edge of a 128 column array would consume a large fraction of the total area of the array. Thus, while it would be desirable to save the huge fraction of chip area which is typically wasted on per-column decoders, it is also desirable not to waste too much chip area on buss lines.
Thus it is an object of the invention to provide a random access memory wherein the total chip area devoted to the column address decoding function, including both logic and buss lines, is minimized.
To accomplish these and other objects, the present invention teaches a column address decoding configuration in which subsets of the column bits are individually decoded. That is, for example, the two least significant bits are separately decoded to provide four buss lines, each of which controls every fourth primary sense amplifier. To each set of four primary sense amplifiers is connected one secondary sense amplifier, and the appropriate secondary sense amplifier is multiplexed onto the output lines by the remainder of the address bits.
Thus, the present invention is the first to teach double multiplexing of sense amplifiers. Multiple primary sense amplifiers are multiplexed together to provide input to each secondary sense amplifier, and multiple secondary sense amplifiers are multiplexed onto the data buss.
The multiplexing referred to is functional multplexing. That is, a conventional multiplex switch matrix may be used, or three state buffers may be connected to a local buss to provide the multiplexing function.
This multiplexing need not be performed in only two stages. For example, to address 64 columns in a subarray, 6 buss lines would be needed with per-column decoders, but, if 12 buss lines are used, three cascaded multiplexing stages according to the present invention can be used instead of the per-column decoder.
A further embodiment of the present invention is the provision of full-decoding for the final sense amplifier, in combination with primary sense amplifiers addressed by the decoded extension of the least significant bits connected to each secondary sense amplifier. That is, for example, a 256-column memory array (8 column address bits), the least significant bits AY0 and AY1 will be separately decoded at the edge of the array into four lines, namely AY0 and AY1, AY0 and not AY1, not AY0 and AY1, and not AY0 and not AY1. For each set of four adjacent columns, the four primary sense amplifiers would each be controlled by exactly one of these four lines. All four primary sense amplifier in each set would be connected to a secondary sense amplifier (one secondary sense amplifier for every four columns). Each secondary sense amplifier could be accessed by a further subset of the decoded address lines, e.g. by lines decoding the states of AY2 and AY3. The remaining four address bits (AY4 thru AY7) could then be used to access decoders spaced across the array but only one of these decoders would be required for every 16 columns. Thus, the total required number of buss lines would be 12 instead 8, and substantial space would be saved on the column decode logic without degrading speed. Alternatively, a full decoder could be used for each 4 or each 8 primary sense amplifiers, to jointly minimize wiring area and logic area.
According to the present invention there is provided:
a random access memory comprising:
an array of memory cells arranged in rows and columns,
a plurality of primary sense amplifiers, each of said columns of said memory cells of said array being connected to exactly one of said primary sense amplifiers,
column Address decoding means, for receiving column address bits and driving first address lines in correspondence with dec oded values of a first subset of said address bits and driving second address lines in correspondence with decoded values of a second subset of said address bits;
a plurality of secondary sense amplifiers, each of said secondary sense amplifiers having an input connected to the outputs of a plurality of primary sense amplifiers, all of said primary sense amplifiers which are connected to a particular one of said secondary sense amplifiers also severally being selectively scheduled by a respective different ones of said first address lines;
said secondary sense amplifier each being selectively activated by exactly one of said second address lines;
at least one output means, connected to said secondary sense amplifiers for providing an output corresponding to the one of said secondary sense amplifiers which has been activated by said second address lines.
According to the present invention there is provided: A random access memory comprising:
an array of memory cells are arranged in rows in columns;
a parality of primary sense amplifiers, each of said primary said amplifiers being connected to one of said columns of said array;
a column addressed decoder, connected to receive a purility column addressed bit and to drive a first said decoder addressed line in correspondence with only a partical subset of said column addressed bits;
a purality of secondary sense amplifiers, each of said secondary sense amplifiers having an input connected to a purality of said primary sense amplifiers, all of said primary sense amplifiers which are connected to each one of said secondary sense amplifiers also severally being selectively activated by respective different ones of said first addressed lines;
said secondary sense amplifiers each being connected to receive signals corresponding to a plurality of said addressed bits of which are not decoded on said first addressed line, said secondary amplifiers each providing an output selectively in accordance with said other addressed bits.